The DVB-S.2 standard, one of the digital satellite broadcasting standards, is among the transmission schemes in which the transmission signal is likely to have a plurality of types of frame lengths. FIG. 1 illustrates the configuration of a transmission signal frame in the DVB-S.2 standard.
A 90-symbol header is placed at the beginning of each frame, followed by a main signal which includes a plurality of slots. Each slot is 90 symbols long. Further, a synchronizing pilot signal may be inserted in the main signal every 16 slots according to the setting.
FIG. 2 illustrates the configuration of a transmission signal header in the DVB-S.2 standard. A header includes a 26-symbol SOF (Start Of Frame) and 64-symbol PLSC (Physical Layer Signaling Code).
The SOF includes a 26-bit fixed value (hereinafter also referred to as the fixed sequence) indicating the beginning of the frame.
The PLSC includes a 64-bit code word obtained by coding 7-bit information indicating a transmission parameter relating to signal transmission into (64,7) Reed-Muller code (RM code). The 7-bit transmission parameter includes 5-bit MODCOD information and 2-bit TYPE information.
The MODCOD information indicates the frame modulation scheme and error correction code coding rate.
The MSB (Most Significant Bit) (hereinafter also referred to as the frame length parameter) of the TYPE information indicates the frame length (in bits). The value “0” (normal) or “1” (short) is set. It should be noted that, in order to facilitate the description, a description will be given below assuming that the frame length parameter does not take on any value other than “0.” Further, the LSB (Least Significant Bit) (hereinafter also referred to as the pilot signal parameter) of the TYPE information indicates the presence or absence of an inserted pilot signal. The value “0” (a pilot signal inserted) or “1” (no pilot signal inserted) is set.
π/2 shift BPSK (Binary Phase Shift Keying) is used as the header modulation scheme. FIG. 3 illustrates a mapping pattern of each symbol of the header in the complex plane. A mapping pattern of an odd-numbered symbol of the header is shown on the left in FIG. 3. A mapping pattern of an even-numbered symbol of the header is shown on the right in FIG. 3. That is, when the value of an odd-numbered symbol is “0,” the symbol is mapped to the point in the complex plane where the argument is π/4. When the value of an odd-numbered symbol is “1,” the symbol is mapped to the point where the argument is 5π/4. When the value of an even-numbered symbol is “0,” the symbol is mapped to the point where the argument is 3π/4. When the value of an even-numbered symbol is “1,” the symbol is mapped to the point where the argument is 7π/4. Therefore, the phase difference between the adjacent symbols is restricted to within the range of ±π/2.
On the other hand, QPSK (Quaternary Phase Shift Keying) or 8PSK (8-ary Phase Shift Keying) is used as the main signal modulation scheme.
Further, the pilot signal contains QPSK unmodulated symbols. That is, each of the symbols of the pilot signal is mapped to the point (1/√2, 1/√2) in the complex plane where the argument is π/4.
FIG. 4 illustrates the types of transmission signal frame lengths in the DVB-S.2 standard. As described above, if the frame length parameter of the TYPE information is fixed to the value “0,” the frame length takes on four types of values depending on the main signal modulation scheme (MOD) and presence or absence of an inserted pilot signal. That is, a frame length L is 33282 symbols when the main signal is modulated by QPSK with an inserted pilot signal. The frame length L is 32490 symbols when the main signal is modulated by QPSK with no inserted pilot signal. The frame length L is 22194 symbols when the main signal is modulated by 8PSK with an inserted pilot signal. The frame length L is 21690 symbols when the main signal is modulated by 8PSK with no inserted pilot signal.
A description will be given here of the frame synchronization in a demodulation circuit adapted to demodulate a signal compliant with the conventional DVB-S.2 standard. It should be noted that the term “frame synchronization” here refers to a sequence of processes adapted to receive a signal containing complex symbol strings (hereinafter also referred to as the input signal), detect the beginning of each frame and output synchronizing signals synchronous with the frames under the effect of interference such as noise or carrier frequency offset. It should be noted that a process may be included in the frame synchronization which is adapted to decode the RM code of the PLSC in the header to obtain MODCOD and TYPE information.
FIG. 5 illustrates a configuration example of a frame synchronization circuit in a demodulation circuit adapted to demodulate a signal compliant with the conventional DVB-S.2 standard described in Patent Document 1. A frame synchronization circuit 11 shown in FIG. 5 includes a differential correlation detector 21 and peak search detector 22.
The differential correlation detector 21 includes a differential calculation section 31, PLSC correlation calculation section 32, SOF correlation calculation section 33, adders 34-1 and 34-2, absolute value calculators 35-1 and 35-2, and selector 36.
The differential calculation section 31 includes a complex conjugate calculator 41, delayer 42, and multiplier 43. The differential calculation section 31 performs differential detection of the input signal and supplies the differential value obtained from the differential detection to the PLSC correlation calculation section 32.
The PLSC correlation calculation section 32 includes delayers 51-1 to 51-64, multipliers 52-1 to 52-32, and an adder 53. The same section 32 calculates, every other symbol, a correlation value indicating the symbol-to-symbol correlation between the symbol string having a differential value of the input signal (hereinafter also referred to as the reception differential sequence) and the symbol string having a correct PLSC differential value (hereinafter also referred to as the PLSC differential sequence), adds up the calculated correlation values and supplies the sum of the correlation values (hereinafter referred to as the PLSC correlation value) to the adders 34-1 and 34-2.
Incidentally, PLSC contains information coded into (64,7) Reed-Muller code (RM code) as described above. The code word of the RM code has the property that if the word is separated from the beginning into 2-bit pairs, the values of the elements of all pairs are either the same or bit-inverted.
Further, whether the values of the elements of all pairs are the same or bit-inverted depends upon the value of a specific bit in the pre-coding data.
In the case of PLSC, if the parameter value of the pilot signal, which is the LSB of the TYPE information in the coded 7-bit transmission parameter of the PLSC, is “0,” the values of the elements of all pairs are the same. The values of all the pairs are either “00” or “11.” If the parameter value of the pilot signal is “1,” the values of the elements of all pairs are bit-inverted. The values of all the pairs are either “01” or “10.” Therefore, the differential values for every other symbol from the beginning of the PLSC differential sequence are all −j (=e−jπ/2) if the parameter value of the pilot signal is “0,” and are all j (=ejπ/2) if the parameter value of the pilot signal is “1.” Thus, the differential values are inverted from each other.
The PLSC correlation calculation section 32 calculates the PLSC correlation value indicating the correlation between the PLSC and reception differential sequences if the parameter value of the pilot signal is “1,” that is, if a pilot signal is inserted in the input signal. Therefore, when the header part of the input signal is fed to the differential correlation detector 21, and the reception differential sequence for the PLSC part of the input signal is fed to the PLSC correlation calculation section 32, the PLSC correlation value is ideally the positive maximum value and negative minimum value, respectively, if the parameter value of the pilot signal is “1” and “0.”
The SOF correlation calculation section 33 includes delayers 61-1 to 61-25, multipliers 62-1 to 62-25, and an adder 63. The SOF correlation calculation section 33 calculates a correlation value indicating the symbol-to-symbol correlation between the reception differential sequence and the symbol string having a correct SOF differential value (hereinafter also referred to as the SOF differential sequence), adds up the calculated correlation values and supplies the sum of the correlation values (hereinafter referred to as the SOF correlation value) to the adders 34-1 and 34-2.
Therefore, the SOF correlation value is ideally the positive maximum value when the header part of the input signal is fed to the differential correlation detector 21, and the reception differential sequence for the SOF part of the input signal is fed to the SOF correlation calculation section 33.
The adder 34-1 adds the PLSC and SOF correlation values together and supplies the sum to the absolute value calculator 35-1.
The adder 34-2 adds together the values inverted in sign from the PLSC and SOF correlation values and supplies the sum to the absolute value calculator 35-2.
The absolute value calculator 35-1 calculates the absolute value of the added value from the adder 34-1 and supplies the absolute value to the selector 36.
The absolute value calculator 35-2 calculates the absolute value of the added value from the adder 34-2 and supplies the absolute value to the selector 36.
The selector 36 selects the greater of the absolute values from the absolute value calculators 35-1 and 35-2 and supplies the value to the peak search detector 22.
Ideally, therefore, if the parameter value of the pilot signal inserted in the input signal is “1,” the absolute value calculated by the absolute value calculator 35-1 and the value output from the selector 36 are maximum when the header part of the input signal is fed to the differential correlation detector 21. If the parameter value of the pilot signal inserted in the input signal is “0,” the absolute value calculated by the absolute value calculator 35-2 and the value output from the selector 36 are maximum when the header part of the input signal is fed to the differential correlation detector 21.
Here, a description will be given of the peak search process performed by the peak search detector 22 with reference to the flowchart shown in FIG. 6.
In step S1, the peak search detector 22 determines whether the modulation scheme is known.
If it is determined that the modulation scheme is known, the process proceeds to step S2.
In step S2, the peak search detector 22 sets a size L of the search window to the frame length appropriate to the known modulation scheme. Then, the process proceeds to step S4.
On the other hand, if it is determined in step S1 that the modulation scheme is not known, the process proceeds to step S3.
In step S3, the peak search detector 22 sets the size L of the search window to the maximum size.
In step S4, the peak search detector 22 finds a position in the search window where the correlation value output from the selector 36 peaks.
In step S5, the peak search detector 22 specifies the found peak position as a candidate.
In step S6, the peak search detector 22 decodes the MODCODE information (MODCOD and TYPE information).
In step S7, the peak search detector 22 derives the position of a next unique word based on the modulation and encoding schemes.
In step S8, the peak search detector 22 verifies whether the position derived in step S7 is actually that of the unique word and MODCODE information.
In step S9, if it is verified successively a predetermined number of times that the derived unique word position is that of the unique word and MODCODE information, the peak search detector 22 declares that frame synchronization has been achieved.
Patent Document 1: Japanese Patent Laid-Open No. 2005-6338